The development cycle for secure integrated circuits (e.g., smart cards) is both time-consuming and costly, as traditional side-channel security assessments are typically conducted only after fabrication (post-silicon). Any flaw discovered at that stage forces a new spin of the entire cycle. Our work instead approaches the security assessment before fabrication—at the pre-silicon stage—by analysing the device directly from its Register Transfer Level (RTL) description. We focus on identifying side-channel leakages and build statistical models that characterise the device’s leakage behaviour, enabling designers to efficiently locate and eliminate the root causes.